LTC2281IUP#PBF【PDF 24/24 页】IC ADC 10BIT DUAL 64-QFN

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Sheet目录2005

20页 21页 22页 23页 [24页]

LTC2281

2281fb

PIN FUNCTIONS

OEA (Pin 58): Channel A Output Enable Pin. Refer to

SHDNA pin function.

SHDNA (Pin 59): Channel A Shutdown Mode Selection

Pin. Connecting SHDNA to GND and OEA to GND results

in normal operation with the outputs enabled. Connecting

SHDNA to GND and OEA to VDD results in normal operation

with the outputs at high impedance. Connecting SHDNA

to VDD and OEA to GND results in nap mode with the

outputs at high impedance. Connecting SHDNA to VDD

and OEA to VDD results in sleep mode with the outputs

at high impedance.

MODE (Pin 60): Output Format and Clock Duty Cycle

Stabilizer Selection Pin. Note that MODE controls both

channels. Connecting MODE to GND selects offset binary

output format and turns the clock duty cycle stabilizer

off. 1/3 VDD selects offset binary output format and turns

the clock duty cycle stabilizer on. 2/3 VDD selects 2’s

complement output format and turns the clock duty cycle

stabilizer on. VDD selects 2’s complement output format

and turns the clock duty cycle stabilizer off.

VCMA (Pin 61): Channel A 1.5V Output and Input Common

Mode Bias. Bypass to ground with 2.2μF ceramic chip

capacitor. Do not connect to VCMB.

SENSEA (Pin 62): Channel A Reference Programming Pin.

Connecting SENSEA to VCMA selects the internal reference

and a ±0.5V input range. VDD selects the internal reference

and a ±1V input range. An external reference greater than

0.5V and less than 1V applied to SENSEA selects an input

range of ±VSENSEA. ±1V is the largest valid input range.

GND (Exposed Pad) (Pin 65): ADC Power Ground. The

Exposed Pad on the bottom of the package needs to be

soldered to ground.

FUNCTIONAL BLOCK DIAGRAM

Figure 1. Functional Block Diagram (Only One Channel is Shown)

SHIFT REGISTER

AND CORRECTION

DIFF

REF

AMP

REF

BUF

2.2μF

1μF

0.1μF

INTERNAL CLOCK SIGNALS

REFH

REFL

CLOCK/DUTY

CYCLE

CONTROL

RANGE

SELECT

1.5V

REFERENCE

FIRST PIPELINED

ADC STAGE

FIFTH PIPELINED

ADC STAGE

SIXTH PIPELINED

ADC STAGE

FOURTH PIPELINED

ADC STAGE

SECOND PIPELINED

ADC STAGE

REFH

REFL

CLK

MODE

OGND

OVDD

2281 F01

INPUT

S/H

SENSE

VCM

AIN

–

AIN

2.2μF

THIRD PIPELINED

ADC STAGE

OUTPUT

DRIVERS

CONTROL

LOGIC

SHDN

OF*

CLKOUT*

*OF AND CLKOUT ARE SHARED BETWEEN BOTH CHANNELS.

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